Scientists from Tohoku University and the University of California, Santa Barbara, have successfully demonstrated a novel computing concept that promises to enhance energy efficiency, particularly for artificial intelligence (AI) applications. This innovative approach incorporates the random operations of miniature spintronic components, making it exceptionally adept for stochastic computational tasks like analysis and random selections.
The findings were unveiled at the prestigious IEEE International Electron Devices Meeting (IEDM 2023) on December 12, 2023. As the rate of advancements defined by Moore’s Law diminishes, the push for specialized computational hardware has become more urgent. Computers that execute calculations probabilistically using inherently random elements known as probabilistic bits, or p-bits, are a prime example, due to their potential to adeptly solve complex problems encountered in machine learning (ML) and AI.
In a similar vein to how quantum computers are perfectly matched to quantum challenges, probabilistic computers at room temperature excel at fundamentally random algorithms. These algorithms play a crucial role in the training of intelligent systems and in tackling difficult tasks related to optimization and random sampling.
The groundbreaking work of the collaborative team demonstrates the feasibility of implementing large-scale and clock-free probabilistic computers. Their creation hinges on a spintronic component known as the stochastic magnetic tunnel junction (sMTJ), combined with versatile Field Programmable Gate Arrays (FPGA).
Until now, computers based on sMTJs had been confined to the functionality of recurrent neural networks. The anticipation has been building for an approach to enable feedforward neural networks, which are critical to most AI applications today.
Professor Kerem Camsari of the University of California, Santa Barbara highlights that extending probabilistic computers to support feedforward neural networks marks a crucial step towards commercial viability and amplified AI processing power.
The breakthrough to be presented at the IEDM 2023 involves two significant technological strides. Firstly, the team has improved upon Tohoku University’s previous work on sMTJs at the device level to achieve the quickest p-bit performance at the circuit level, with fluctuations occurring roughly every microsecond, a thousandfold improvement.
Secondly, the researchers have implemented a new processing sequence within the hardware, adopting parallel processing across layers, to showcase an example of how a Bayesian network – a type of feedforward stochastic neural network – operates.
According to Professor Shunsuke Fukami from Tohoku University, although the prototypes are currently on a smaller scale, there’s potential for upscaling by utilizing CMOS-compatible Magnetic RAM (MRAM) technology. This would offer significant enhancements to machine learning applications and potentially pave the way for efficient implementation of complex deep and convolutional neural network hardware.